© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 6
1
Publication Order Number:
MTD5P06V/D
MTD5P06V
Preferred Device
Power MOSFET
5 Amps, 60 Volts P−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
Features
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Pb−Free Packages are Available
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
Vdc
Drain−to−Gate Voltage (RGS = 1.0 MΩ)
VDGR
60
Vdc
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tp ≤ 10 ms)
VGS
VGSM
± 15
± 25
Vdc
Vpk
Drain Current − Continuous @ 25°C
− Continuous @ 100°C
− Single Pulse (tp ≤ 10 μs)
ID
ID
IDM
5
4
18
Adc
Apk
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 2)
PD
40
0.27
2.1
W
W/°C
W
Operating and Storage Temperature Range
TJ, Tstg
−55 to
175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak
IL = 5 Apk, L = 10 mH, RG = 25 Ω)
EAS
125
mJ
Thermal Resistance
Junction−to−Case
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
RθJC
RθJA
RθJA
3.75
100
71.4
°C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 seconds
TL
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR−4 board using the 0.5 sq in drain pad size.
D
S
G
P−Channel
Preferred devices are recommended choices for future use
and best overall value.
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60 V
340 mΩ
RDS(on) TYP
5.0 A
ID MAX
V(BR)DSS
1
Gate
3
Source
2
Drain
4
Drain
DPAK
CASE 369C
STYLE 2
MARKING
DIAGRAM
Y
= Year
WW
= Work Week
5P06V = Device Code
G
= Pb−Free Package
1 2
3
4
Device
Package
Shipping†
ORDERING INFORMATION
MTD5P06V
DPAK
75 Units/Rail
MTD5P06VT4
DPAK
2500/Tape & Reel
YWW 5 P06VG
MTD5P06VT4G
DPAK
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
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2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
60
−
−
61.2
−
−
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
−
−
−
−
10
100
μAdc
Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc)
IGSS
−
−
100
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
(VDS = VGS, ID = 250 μAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
2.0
−
2.8
4.7
4.0
−
Vdc
mV/°C
Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 2.5 Adc)
RDS(on)
−
0.34
0.45
Ω
Drain−Source On−Voltage
(VGS = 10 Vdc, ID = 5 Adc)
(VGS = 10 Vdc, ID = 2.5 Adc, TJ = 150°C)
VDS(on)
−
−
−
−
2.7
2.6
Vdc
Forward Transconductance
(VDS = 15 Vdc, ID = 2.5 Adc)
gFS
1.5
3.6
−
Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Ciss
−
367
510
pF
Output Capacitance
Coss
−
140
200
Transfer Capacitance
Crss
−
29
60
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
(VDD = 30 Vdc, ID = 5 Adc,
VGS = 10 Vdc, RG = 9.1 Ω)
td(on)
−
11
20
ns
Rise Time
tr
−
26
50
Turn−Off Delay Time
td(off)
−
17
30
Fall Time
tf
−
19
40
Gate Charge
(See Figure 8)
(VDS = 48 Vdc, ID = 5 Adc, VGS = 10 Vdc)
QT
−
12
20
nC
Q1
−
3.0
−
Q2
−
5.0
−
Q3
−
5.0
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 5 Adc, VGS = 0 Vdc)
(IS = 5 Adc, VGS = 0 Vdc, TJ = 150°C)
VSD
−
−
1.72
1.34
3.5
−
Vdc
Reverse Recovery Time
(IS = 5 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/μs)
trr
−
97
−
ns
ta
−
73
−
tb
−
24
−
Reverse Recovery Stored Charge
QRR
−
0.42
−
μC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
LD
−
4.5
−
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
−
7.5
−
nH
3. Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.
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TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS)
R
DS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
0
1
2
3
4
5
0
7
2
4
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
ID
, DRAIN CURRENT (AMPS)
7
8
2
3
4
8
0
1
2
3
6
ID
, DRAIN CURRENT (AMPS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
1
2
3
4
5
6
0.2
0.25
0.3
0.35
0.6
R
DS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS)
1
2
3
4
5
7
0.2
8
0.25
0.3
0.4
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
−50
1.8
0.2
0.4
0.6
0
10
20
30
40
1
50
10
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−To−Source Leakage
Current versus Voltage
IDSS
, LEAKAGE (nA)
TJ = 125°C
15 V
−25
0
25
50
75
100
150
TJ = 25°C
VDS ≥ 10 V
TJ = −55°C
25°C
100°C
TJ = 100°C
25°C
−55°C
TJ = 25°C
VGS = 0 V
VGS = 10V
VGS = 10 V
VGS = 10 V
VGS = 10 V
ID = 2.5 A
6
8
6
7 V
6 V
5 V
4 V
8 V
9 V
4
5
5
6
7
0.4
0.45
7
0.35
9
6
0.8
1
1.2
1.4
1.6
125
60
8
9
9
10
8
9
10
0.5
0.55
10
175
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4
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
10
0
5
10
15
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
Figure 7. Capacitance Variation
VGS
VDS
Ciss
Coss
Crss
TJ = 25°C
VDS = 0 V
VGS = 0 V
600
500
400
300
200
100
5
0
20
25
Ciss
Crss
700
800
900
1000
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VDS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
0.2
0.4
0.6
0.8
1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
I S
, SOURCE CURRENT (AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE (OHMS)
1
10
100
t, TIME (ns)
TJ = 25°C
ID = 5 A
VDD = 30 V
VGS = 10 V
tr
tf
td(off)
td(on)
TJ = 25°C
VGS = 0 V
Figure 10. Diode Forward Voltage versus Current
0
Qg, TOTAL GATE CHARGE (nC)
2
4
6
8
12
TJ = 25°C
ID = 5 A
VDS
VGS
0
0.5
1
1.5
3
100
10
1
9
7
5
0
10
8
6
4
60
30
24
18
12
6
0
3
2
1
10
36
42
48
54
Q2
Q3
QT
Q1
2
2.5
1.2
1.4
1.6
1.8
14
3.5
4
4.5
5
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain−to−source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance−General
Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
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6
SAFE OPERATING AREA
TJ, STARTING JUNCTION TEMPERATURE (°C)
EAS
, SINGLE PULSE DRAIN−TO−SOURCE
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
AVALANCHE ENERGY
(mJ)
ID
, DRAIN CURRENT (AMPS)
25
50
75
100
125
ID = 5 A
150
Figure 13. Thermal Response
r(t), NORMALIZED EFFECTIVE
TRANSIENT
THERMAL RESISTANCE
Figure 14. Diode Reverse Recovery Waveform
di/dt
trr
ta
tp
IS
0.25 IS
TIME
IS
tb
0
60
80
0.1
100
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10
VGS = 20 V
SINGLE PULSE
TC = 25°C
1
1
10
100
0.1
dc
100 μs
1 ms
10 ms
40
20
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RθJC(t)
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
t, TIME (s)
1.0
0.1
0.01
0.2
D = 0.5
0.05
0.01
SINGLE PULSE
0.1
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
1.0E+00
1.0E+01
0.02
100
120
140
175
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7
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.235
0.245
5.97
6.22
B
0.250
0.265
6.35
6.73
C
0.086
0.094
2.19
2.38
D
0.027
0.035
0.69
0.88
E
0.018
0.023
0.46
0.58
F
0.037
0.045
0.94
1.14
G
0.180 BSC
4.58 BSC
H
0.034
0.040
0.87
1.01
J
0.018
0.023
0.46
0.58
K
0.102
0.114
2.60
2.89
L
0.090 BSC
2.29 BSC
R
0.180
0.215
4.57
5.45
S
0.025
0.040
0.63
1.01
U
0.020
−−−
0.51
−−−
V
0.035
0.050
0.89
1.27
Z
0.155
−−−
3.93
−−−
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
D
A
K
B
R
V
S
F
L
G
2 PL
M
0.13 (0.005)
T
E
C
U
J
H
−T− SEATING
PLANE
Z
1
2
3
4
5.80
0.228
2.58
0.101
1.6
0.063
6.20
0.244
3.0
0.118
6.172
0.243
mm
inches
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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