Leakage current, active power, and delay analysis of dynamic dual
Vt CMOS
circuits under
P–
V–
T fluctuations
Jinhui Wang a,*
, Na Gong b, Ligang Hou a, Xiaohong Peng a, Ramalingam Sridhar b, Wuchen Wu a
a
VLSI and System Lab, Beijing University of Technology, Beijing 100124, China
b
Department of Computer Science and Engineering, SUNY at Buffalo, Buffalo, NY 14260, USA
a r t i c l e i n f o
Article history:
Received 29 May 2011
Received in revised form 9 June 2011
Accepted 10 June 2011
Available online 13 July 2011
a b s t r a c t
The leakage current, active power and delay characterizations of the dynamic dual
Vt CMOS circuits in the
presence of process, voltage, and temperature (
P–
V–
T) fluctuations are analyzed based on multiple-
parameter Monte Carlo method. It is demonstrated that failing to account for
P–
V–
T fluctuations can
result in significant reliability problems and inaccuracy in transistor-level performance estimation. It also
indicates that under significant
P–
V–
T fluctuations, dual
Vt technique (DVT) is still highly effective to
reduce the leakage current and active power for dynamic CMOS circuits, but it induces speed penalty.
At last, the robustness of different dynamic CMOS circuits with DVT against the
P–
V–
T fluctuations is dis-
cussed in detail.
© 2011 Elsevier Ltd. All rights reserved.
1. Introduction
Dynamic CMOS circuits or similar structures are extensively
employed in high performance microprocessors and memory [1,2]
due to the superior speed and area characteristics. However, along
with the progress of advanced VLSI technology, the reduction of
the threshold voltage (
Vt) and gate oxide thickness (
tox) leads to
the exponential increase in the sub-threshold leakage current (
Isub)
and gate leakage current (
Igate), which become a major design chal-
lenge. Moreover, in most of current electronic equipments, the clock
frequency has been over 1 GHz, which leads to a linear increase in
the active power.
The dual
Vt technique (DVT) proposed in [3] has been proved to
be extremely effective in suppressing
Isub of the dynamic CMOS
circuits by assigning low
Vt devices in the evaluation path and high
Vt devices in the pre-charge path, respectively, as shown in Fig. 1.
And in the evaluation phase of the dynamic CMOS circuits, the
active power contains two parts: dynamic switching power and
leakage current power. Therefore, DVT is also an effective tech-
nique to decrease the active power.
However, as the technology scales down below 65 nm node, due
to the increasing die-to-die and with-in chip fluctuations, new reli-
ability problems are coming into effect. These emerging reliability
issues result in device performance degradation and system opera-
tion failure. There are three main contributors to fluctuations. They
are changes in process parameters, in operating temperatures, and
in supply voltage. Process fluctuations occur due to proximity effects
in photolithography, non-uniform conditions during deposition and
random dopant fluctuation. They result in the fluctuation in
Vt which
determines the leakage current, active power, and delay of the cir-
cuits. Changes in the operating temperature occur because of power
dissipation in the form of heat. On-chip thermal fluctuations have a
significant bearing on the mobility of electrons and holes, as well as
Vt of the devices. And, the leakage current has a linear dependence on
the supply voltage swing. Therefore, in nano-scale CMOS technolo-
gies, process, voltage, and temperature (
P–
V–
T) fluctuations are
crucial reliability concerns. There exists the need to estimate the
dynamic CMOS circuit performance under
P–
V–
T fluctuations to
help designers judge if the DVT application could meet the reliability
related frequency-leakage-power requirements in sub-65 nm era.
Although many researchers have quantified the impact of
P–
V–
T
fluctuations on circuits, there is no known work that has sufficiently
described the combined effects of
P–
V–
T fluctuations on leakage
current, active power, and delay characteristics. In [4] a full-chip
leakage considering uneven voltage drop and uneven temperature
is estimated, but it is not a probabilistic approach. In [5] the impact
of channel length fluctuations on
Isub is studied, but its analysis is
based on an empirical relationship between the leakage and the
channel length. Moreover, the analysis in [5] cannot be easily
extended to
P–
V–
T fluctuations. Although, the work presented in
[6–8] develop statistical models to estimate leakage under fluctua-
tions, they fail to account for the combined effects of
P–
V–
T fluctu-
ations. In addition, due to the approximations involved, these
analyses are inaccurate as compared to the simulations based on
BSIM4 models. Moreover, these models cannot provide the
probability distribution function of leakage current. [9–11] have
presented leakage characterization under
P–
V–
T fluctuations;
0026-2714/$ - see front matter © 2011 Elsevier Ltd. All rights reserved.
doi:10.1016/j.microrel.2011.06.011
* Corresponding author. Tel.: +86 (10) 67391638 23; fax: +86 (10) 67391638 22.
E-mail address: wangjinhui@bjut.edu.cn (J. Wang).
Microelectronics Reliability 51 (2011) 1498–1502
Contents lists available at ScienceDirect
Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel
however, none of them take the strong coupling between the leak-
age and the temperature into consideration. In [12], the impact of
P–
V–
T fluctuations on leakage is accurately modeled, but active
power and delay characterizations are not mentioned. The analysis
in [13] only refers to dynamic CMOS OR gates, and the process var-
iation model assumes that there is a uniform 10% variation in
Leff,
Nch, and
tox, which is not reliable enough to account for the process
variation.
In this paper, utilizing statistical method – multiple parameter
Monte Carlo simulation, the leakage current, active power, and de-
lay characteristics in various dynamic CMOS circuits with DVT is
analyzed in the presence of simultaneous
P–
V–
T fluctuations based
on the latest ITRS variation model [14].
This paper is organized as follows: in Section 2, the important
factors influencing the leakage current, active power and delay
characteristics of dynamic circuits is discussed. Section 3 evaluates
the effectiveness of DVT under
P–
V–
T variations in detail. Section 4
concludes this work.
2. Dynamic dual Vt
CMOS circuits
In this section, the leakage current, active power and delay
characteristics of dynamic circuits are discussed analytically.
2.1. Delay time
If we do not consider the delay of the input signal, the delay of
dynamic gates can be expressed as [15]
tdelay ¼
Ceval Б
Vdd
2
IDSAT
¼
CP1
GD ю
CP2
GD ю
CPDN
GD ю
Cinv
G
ю
Cload
(
)
Б
Vdd
2
kn Б р
Weff /
Leff Юр
VGS А
VtЮa
р1Ю
where
Ceval is the capacitance of the evaluation node;
IDSAT is the sat-
uration current;
CP1
GD,
CP2
GD,
CPDN
GD ,
Cinv
GD,
Cload are gate–drain capacitance
of the precharger P1, the keeper P2, PDN, the inverter connected to
keeper, and loading capacitance (see Fig. 1), respectively;
kn is a
technology parameter; a is the velocity saturation exponent ranges
from 1 to 2;
Weff is the width of the transistors.
Noted that,
CPDN
GD
is dependent on the fan-in number and PDN
structure of a dynamic circuit. In addition, since DVT adopts high
Vt transistors,
IDSAT is smaller, thereby inducing larger delay time.
2.2. Leakage current
To achieve minimum
Isub in the sleep state, the dual
Vt dynamic
gates are set in CHIH (CLK = 1, In1 = In2 = , ... , In
N = 1) state [3].
Accordingly, the leakage current (
Ileak) can be expressed as [13,16]
Ileak ¼
Isub ю
Igate ¼
∑
i
½
WHNЉi Б
JSHN ю
∑
j
½
WHPЉ
j Б
JSHP ю
WLN Б
JGFLN
ю
1
2
Б
∑
i
½
WHNЉi Б
JGRHN ю
IPDN
gate
р2Ю
where
JSHN,
JSHP,
JGFLN,
JGRHN are
Isub density per width unit of high
Vt
NMOS, high
Vt PMOS, forward
Igate density per width unit of low
Vt
NMOS, reverse
Igate density per width unit of high
Vt NMOS, respec-
tively;
WHN,
WHP,
WLN are gate widths of high
Vt NMOS, high
Vt PMOS,
low
Vt NMOS (see Fig. 1), respectively;
IPDN
gate is the
Igate generated by
PDN, which dominates the total
Igate of the dynamic circuit and
depends on the fan-in number and PDN structure.
2.3. Active power
The active power is composed of dynamic switching power and
leakage current. This subsection focuses on the dynamic switching
power. In a dynamic circuit, the dynamic switching power is con-
sumed to charge and discharge the keeper, the evaluation node and
the devices in PDN. Accordingly, it can be expressed as [15]:
Pdynamic ¼
V2
dd Б
Ceval ю
CINV
GD ю
CPDN
G
ю
CP2
G
(
)
р3Ю
where
CINV
GD ,
CPDN
G
,
CP2
G
are gate–drain capacitance of the output inver-
ter, the gate capacitance of PDN and the keeper P2, respectively.
CPDN
G
varies with the fan-in number and PDN structure of dynamic
circuits.
As given by (1)–(3), the leakage current, active power and delay
characteristics of dynamic gates depends on the design parameters
(such as fan-in number, size of devices, PDN structure), environ-
mental parameters (such as temperature and supply voltage) and
the manufacturing technologies. In the following section, consider-
ing these factors, we will present a quantitative analysis to inves-
tigate the influence of
P–
V–
T fluctuations on leakage current,
active power, and delay characteristics of the dynamic CMOS
circuits with DVT.
3. Effectiveness of dual Vt
technique under PVT variations
In our analysis, the dynamic circuits with different fan-in
numbers and PDN structures, including 2-input, 4-input, 8-input,
and 16-input dynamic OR gate (OR2, OR4, OR8, and OR16, respec-
tively), 2-input and 8-input dynamic AND gates (AND2 and AND8),
2-input and 16-input dynamic multiplexer (MUX2 and MUX16),
are employed as the benchmark circuits. They are simulated based
on 45 nm BSIM4 models by the HSPICE tool [17,18]. The parameters
of devices are listed in Table 1. Each dynamic gate drives a capacitive
load of 8 fF.
P1
P3
P4
N1
N2
footer
CLK
Vdd
Vdd
Evaluation node
in1
in2
inN
Output
Cload
Vdd
Vdd
Pull Down Network (PDN)
P2
P1
P3
P4
N1
N2
footer
CLK
Vdd
Vdd
Evaluation node
in1
in2
inN
Output
Cload
Vdd
Vdd
Pull Down Network (PDN)
P2
High Vt devices
Low Vt devices
(a)
(b)
Fig. 1. Dynamic gates. (a) Low
Vt dynamic gate. (b) Dual
Vt dynamic gate.
J. Wang et al. / Microelectronics Reliability 51 (2011) 1498–1502
1499
The sizing of transistors in different gates is based on two
important criteria: all gates are sized to operate at 1 GHZ clock fre-
quency; for the same gates with dual
Vt and low
Vt techniques, the
transistors have the same size, which provides the fair basis of
characteristics comparison of two techniques.
Our analysis is based on the
P–
V–
T variations specified by latest
International Technology Roadmap for Semiconductors (ITRS) [14],
which is also listed in Table 1. the process parameters
Leff,
tox, and
Vt, and
Vdd are all assumed to have normal Gaussian statistical dis-
tributions with a three sigma (3r) fluctuations of 12%, 5%, 40%, and
10%, respectively.
Since temperature variation in practical sleep circuits depends
on the interval of sleep mode, and dynamic circuits are typically
used in high activity area such as register files, our analysis consid-
ers the sleep circuits with short standby intervals and the sleep
temperature of circuits will change from the typical working tem-
perature 110 °C to room temperature. Thousand multiple parame-
ter Monte Carlo simulations are done to achieve enough statistical
accuracy.
3.1. Leakage current, active power and delay characteristics under PVT
variations
In this subsection, the leakage current, active power and delay
characteristics of dual
Vt dynamic gates are discussed. Fig. 2 shows
the distribution curves of 16-input MUX gates with DVT and low
Vt
techniques as an example. It can be seen that the leakage current
distribution curves of two MUX gates cross at 1760 nA. The leakage
current of 77% of the samples with DVT is lower than 1760 nA.
Alternatively, 57% of the low
Vt samples generate leakage current
higher than 1760nA. These results indicate that DVT is highly
effective to reduce the total leakage current even under significant
P–
V–
T fluctuations. Also, two active power distribution curves
intersect at 22.9 lW. The active power consumption of 71% of
the dual
Vt samples is lower than 22.9 lW and 86% of the low
Vt
samples consume active power higher than 15 lW. This is because
DVT can be effective to suppress the leakage power, thereby reduc-
ing the total active power. As also can be seen from Fig. 2, the delay
time of 94% MUX16 sample gates with low
Vt technique is smaller
than 0.42 ns, while 98% of dual
Vt samples is larger than 0.42 ns.
Obviously, under the effect of
P–
V–
T fluctuations, the inferior
speed characteristics of the high
Vt transistors in circuit with
DVT still induce the speed penalty, as discussed in Section 2.
Table 2 lists the leakage current, active power, and delay charac-
teristics of OR2, OR4, OR8, OR16, AND2, AND8, MUX2, and MUX16
dynamic gates under
P–
V–
T variations. As indicated, as to leakage
power and active power, over 50% samples of all of the dual
Vt
dynamic gates are smaller than the cross points, and alternatively
over 50% samples of all of the low
Vt dynamic gates are larger than
the cross points. Therefore, under the effect of
P–
V–
T fluctuations,
DVT is still quite effective to reduce the total leakage and active
power consumption for all style of dynamic gates with speed loss.
3.2. Robustness comparison
This subsection analyzes the robustness (l/r – average/stan-
dard deviations) of leakage current, active power and delay charac-
teristics of dynamic circuits with DVT. To compare the robustness
of two techniques, we also calculate the improvement of robust-
ness with DVT as compared to that with low
Vt technique using
the following equation:
robustness % ¼
robust@
DVT А
robust@
low vt
robust@
low vt
р4Ю
where
robust@DVT and
robust@low_vt represent the robustness
with DVT and low
Vt
technique, respectively. Obviously, if
robustness % P 0, then DVT improves the robustness of dynamic
Table 1
Parameter of devices and
P–
V–
T variations.
Technology node
45 nm BSIM4
Low
Vt
High
Vt
Device parameters
NMOS
Vt
0.22 V
0.35 V
PMOS
Vt
А0.22 V
А0.35 V
Vdd
0.8 V
P–V–T variations
Process (3r)
Leff
12%
tox
5%
Vt
40%
Vdd (3r)
10%
Temperature
110–25 °C
0
0.2
0.4
0.6
0.8
1
1.2
x 10-9
0
50
100
150
200
250
300
Delay time (s)
Number of Samples
45nm MUX16
Dual Vt
Low Vt
0.42 ns
94%
98%
μ=0.561 σ=0.085
μ=0.365
σ=0.033
1.5
2
2.5
3
3.5
x 10-5
0
20
40
60
80
100
120
Active Power (W)
Number of Samples
45nm MUX16
Dual Vt
Low Vt
2.29
71%
86%
μ= 2.17
σ= 0.20
μ= 2.48
σ= 0.20
0
2000
4000
6000
8000
0
50
100
150
Leakage Current (nA)
Number of Samples
45nm MUX16
Dual Vt
Low Vt
1760 nA
77%
57%
μ= 2559
σ= 803
μ= 1552
σ= 370
Fig. 2. Leakage current, active power, and delay distribution of 4-input dual
Vt
dynamic OR gate.
1500
J. Wang et al. / Microelectronics Reliability 51 (2011) 1498–1502
circuits; otherwise, adopting DVT will degrade the robustness of
circuits.
Table 3 lists the comparison result. We can see that the leakage
current robustness of all dual
Vt gates are larger than that of the
low
Vt gates, which shows that DVT can sustain the availability
of suppressing leakage current with
P–
V–
T fluctuations. Also ob-
served in Table 3, the delay robustness in all dynamic gates with
DVT are lower than that of the low
Vt gates. Therefore, while induc-
ing delay penalty, DVT also degrades the immunity of delay char-
acteristics to
P–
V–
T fluctuation.
Another important observation in Table 3 is that, for all circuits
with DVT other than OR2, the active power robustness is lower as
compared to their low
Vt counterparts. But, as discussed in Section
3.1, DVT is able to reduce the active power of all gates effectively
under
P–
V–
T variations. Therefore, the influence of DVT on overall
active power characteristics of dynamic circuits depends on the
power reduction, the robustness degradation, and the relative
significance of these two factors. Accordingly, to evaluate the
overall active power characteristics, we define Improvement-
of-DVT (DVT %) as
DVT % ¼ k В
Power Reduction% ю р1 А kЮ В
robustness%
р5Ю
where k is the weighting factor, which indicates the significance of
active power reduction and active power robustness in different
application cases. Clearly, k is a real number and k e [0, 1]. In partic-
ular, in the extreme case with k = 1, the active power reduction is
Table 2
The average (l) and standard deviations (r) of the dynamic gates (leakage: leakage power; active: active power; delay: delay).
Different circuits
Monte Carlo result
Characteristics of distribution curves
Leakage (nA)
Active (10А5 W)
Delay (10А10 s)
Leakage (nA)
Active (10А5 W)
Delay (10А10 s)
l
r
l
r
l
r
Cross
6 (%)
> (%)
Cross
6 (%)
> (%)
Cross
6 (%)
> (%)
OR2
Dual
Vt
195
65.8
1.33
0.15
5.99
0.89
247.7
95
5
1.38
70
30
4.72
4
96
Low
Vt
660
574
1.56
0.18
4.25
0.36
26
74
17
83
93
7
OR4
Dual
Vt
281
79.4
1.37
0.16
6.15
0.93
324.9
83
17
1.43
71
29
4.73
6
94
Low
Vt
747
584
1.61
0.17
4.19
0.36
21
79
16
84
96
4
OR8
Dual
Vt
452
113
1.51
0.19
6.53
0.95
518.4
82
18
1.56
70
30
5.13
4
96
Low
Vt
920
607
1.75
0.19
4.48
0.39
26
74
19
81
95
5
OR16
Dual
Vt
872
208
1.90
0.19
5.15
0.85
988
76
24
1.93
61
39
3.69
3
97
Low
Vt
1373
605
2.13
0.20
3.18
0.29
33
67
16
84
97
3
AND2
Dual
Vt
560
136
1.81
0.31
6.73
0.90
684.3
87
13
1.82
60
40
5.17
3
97
Low
Vt
1033
626
2.06
0.26
4.45
0.38
37
63
17
83
96
4
AND8
Dual
Vt
1852
434
2.03
0.36
7.87
0.87
2084
75
25
2.08
68
32
6.50
4
96
Low
Vt
2382
907
2.33
0.41
5.90
0.38
45
55
33
67
95
5
MUX2
Dual
Vt
282
79.6
2.19
0.18
5.44
0.73
324.9
83
27
2.25
71
29
4.54
9
91
Low
Vt
750
560
2.44
0.20
4.11
0.36
20
80
16
84
91
9
MUX16
Dual
Vt
1552
370
2.17
0.20
5.61
0.85
1760
77
23
2.29
71
29
4.20
2
98
Low
Vt
2559
803
2.48
0.20
3.65
0.33
43
57
14
86
94
6
Table 3
The robustness of dynamic gates.
Circuits
Leakage current
Active power
Delay time
Robustness
Robustness (%)
Robustness
Robustness (%)
Robustness
Robustness (%)
Dual
Vt
Low
Vt
Dual
Vt
Low
Vt
Dual
Vt
Low
Vt
OR2
2.96
1.15
158
8.87
8.67
2.30
6.73
11.81
А43.0
OR4
3.54
1.28
177
8.56
9.47
А9.59
6.61
11.64
А43.2
OR8
4.00
1.52
164
7.95
9.21
А13.7
6.87
11.49
А40.2
OR16
4.19
2.27
85
10.00
10.65
А6.10
6.06
7.48
А44.7
AND2
4.12
1.65
150
5.84
7.92
А26.3
7.48
11.71
А36.1
AND8
4.27
2.63
62
5.64
5.68
А0.77
9.05
15.53
А41.7
MUX2
3.54
1.34
165
12.17
12.5
А0.27
7.45
11.42
А34.7
MUX16
4.19
3.19
32
10.85
12.4
А12.5
6.60
11.06
А40.3
Fig. 3. Active power characteristics of dynamic circuits.
J. Wang et al. / Microelectronics Reliability 51 (2011) 1498–1502
1501
the only design concern.
Power_Reduction% is used to evaluate the
active power reduction and it can be expressed as
Power Reduction% ¼
power@
low vt А
power@
DVT
power@
low vt
р6Ю
where
powert@DVT and
power@low_vt represent the active power
with DVT and low
Vt technique (see Table 2), respectively.
Note that, if DVT% P 0, the overall active power characteristics
of dynamic circuits is improved with DVT under PVT variations.
Fig. 3 shows the DVT% as a function of k in different gates. We
can see that for all circuits, the DVT% increases with the increasing
of k. This is because, the priority of power reduction becomes high-
er as k increases, and therefore DVT is more likely to improve the
overall active power characteristics. As also can be observed in
Fig. 3, the minimum k value that can achieve improvement of over-
all active power characteristics (DVT% = 0) is between 0.745 and
0.805, depending on the fan-in number and the PDN structure.
For the low fan-in OR gates with DVT (OR2, OR4 and OR8), they
show best active power characteristics; for high fan-in OR gates
(OR16) and all MUX gates (MUX2 and MUX8) with DVT, they show
worst active power characteristics.
4. Conclusion
Due to the increasing die-to-die and with-in chip fluctuations,
new reliability problems are coming into effect. These emerging
reliability issues result in device performance degradation and sys-
tem operation failure. In this paper, under significant
P–
V–
T fluctu-
ations, the effectiveness of DVT in dynamic logic design is analyzed
based on multiple-parameter Monte Carlo simulation. Our analysis
shows that DVT is highly effective to reduce the leakage current
and active power consumption in dynamic gates with speed loss.
Also, DVT can improve the robustness and heighten the reliability
of leakage current in dynamic gates to
P–
V–
T fluctuations. How-
ever, DVT degrade the reliability of obtaining constant active
power and delay. That is it weakens the immunity of active power
and delay characteristics to
P–
V–
T fluctuation. Considering both
the active power reduction and robustness degradation, DVT can
improve the overall active power characteristics when the relative
significance of these two factors is larger than 4.13 (0.805/0.195),
therefore DVT has superior reliability to
P–
V–
T fluctuations. The re-
sults are a good guide to dynamic logic design with DVT taking reli-
ability issues into account.
In future work, we will tape out enough chips and test them to
confirm our simulation results with experiments. Another possible
area for future investigation is to design novel dynamic dual
Vt cir-
cuit to improve the timing yield.
Acknowledgments
This work is supported by the Startup Foundations for Doctors of
BJUT (Nos. X0002013201103, X0002012200802, and X0002014-
201101) and the National Natural Science Foundation of China
(No. 60976028).
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